Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus

ABSTRACT

A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer  2  for controlling a plurality of semiconductor device testing apparatus  1 A,  1 B, and  1 C, and a dedicated classifying machine  3.  Storage information memory means  4  for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer  2.  Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part  11  of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means. When all the tests are completed, the storage information of each device stored in the storage information memory means is transmitted to the dedicated classifying machine by which the tested devices are sorted out.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device testingapparatus suitable for testing one or more semiconductor devices,particularly one or more semiconductor integrated circuit elements (aswill be referred to as IC or ICs hereinafter) which are typical examplesof the semiconductor devices. More particularly, the present inventionrelates to a semiconductor device testing apparatus of the type in whichsemiconductor devices to be tested are transported, for testing, to atest or testing section where they are brought into electrical contactwith a tester head (a component of the testing apparatus for applyingand receiving various electrical signals for testing) to perform anelectrical test of the semiconductor devices, followed by being carriedout of the test section and then the tested semiconductor devices aresorted out into conformable or pass articles and unconformable orfailure articles on the basis of the test results, and a semiconductordevice testing system having a plurality of such semiconductor devicetesting apparatus.

BACKGROUND ART

[0002] Many of semiconductor device testing apparatus (commonly calledIC tester) for applying a test signal of a predetermined pattern to asemiconductor device to be tested, i.e. device under test (commonlycalled DUT) and measuring the electrical characteristics of the devices,have a semiconductor device transporting and handling or processingapparatus (commonly called handler) mounted thereto which transportssemiconductor devices to a test section, brings them into electricalcontact with a tester head in the test section, after the testing,carries the tested semiconductor devices out of the test section, andsorts them out into pass articles and failure articles on the basis ofthe test results. In the specification, the testing apparatus whichcomprises a combination of the IC tester and the handler mounted orconnected thereto of the type described above is termed “semiconductordevice testing apparatus”. In the following disclosure the presentinvention will be described by taking ICs typical of semiconductordevices for example for clarity of explanation.

[0003] As the density of elements integrated on a semiconductorsubstrate or chip in an IC becomes higher, the number of terminals orpins of the IC is increased, and it is difficult to test such an IChaving a large number of terminals using an IC testing apparatus havinga naturally dropping type handler mounted thereto in which ICs arecaused to slide down in a sloped carrying path or groove by theirgravities for testing the ICs. Therefore, the general trend in recentyears is toward the use of an IC testing apparatus having a handlercalled “horizontal transporting system” mounted thereto which cantransport ICs to any desired place or position by using suction headmeans utilizing a vacuum pump which may pick up one to several ICs at atime and X and Y direction transfer means.

[0004] There have been previously used in practice following two typesof IC testing apparatus each having a horizontal transporting systemhandler mounted thereto.

[0005] (1) One type of the IC testing apparatus is arranged such that atray on which many ICs are loaded in a plane is placed at apredetermined position of the testing apparatus, a predetermined numberof ICs are picked up by suction from the tray by use of a suction headutilizing a vacuum pump (vacuum suction head), the ICs being attractedagainst the vacuum suction head are transported to a test sectionthrough a preheating/precooling section by use of X and Y directiontransfer means for testing, and upon completion of the test the testedICs are sorted out into conformable articles (pass articles) andunconformable articles (failure articles), and transferred onto thecorresponding trays by use of X and Y direction transfer means.

[0006] (2) The other type of the IC testing apparatus is arranged suchthat many ICs are loaded in a plane on a general-purpose tray (customertray) which is used by a user for conveying ICs or storing ICs at apredetermined place or the like in the outside of the testing apparatus,the general-purpose tray with the ICs loaded is placed at a loadersection of the testing apparatus where the ICs are transferred from thegeneral-purpose tray onto a test tray capable of withstanding high/lowtemperatures, the test tray is transported through a constanttemperature chamber or thermostatic chamber to a test section where ICsare brought into electrical contact with a tester head in the state thatthey are being loaded on the test tray for performing a test, and uponcompletion of the test the test tray with the tested ICs loaded aretransported through a temperature-stress removing chamber to an unloadersection where the tested ICs are sorted out into pass articles andfailure articles and transferred onto the corresponding trays to bereloaded thereon.

[0007] The IC testing apparatus having a handler of the former type (1)mounted thereto has a disadvantage that since the number of ICs whichundergo a test at a time is limited to two to four, the processing speedis low, and hence a considerable time is required to test all ICs. Thatis, the IC testing apparatus of the type (1) is not suitable forprocessing at high speed. On the other hand, the IC testing apparatushaving a handler of the latter type (2) mounted thereto has an advantagethat since ICs can be brought into electrical contact with a tester headof the testing apparatus in the state that they are being loaded on thetest tray in the test section, it is possible to test many of ICs suchas 16, 32 or 64 at a time. Therefore, at present, an IC testingapparatus having a handler of the latter type (2) mounted thereto isbeing mainly used.

[0008] A description will be given first regarding the generalconstruction of a conventional IC testing apparatus having a handler ofthe latter type (2) mounted thereto with reference to FIGS. 4 and 5. Theillustrated IC testing apparatus comprises a chamber section 100 fortesting ICs such as semiconductor memories which are loaded on a testtray TST and carried on the test tray TST, an IC storage section 200where ICs which will undergo a test (i.e., ICs to be tested) are sortedout and the tested ICs are sorted out and stored in place, a loadersection 300 where ICs to be tested which a user has beforehand loaded ona general-purpose tray (customer tray) KST are transferred and reloadedonto a test tray TST capable of withstanding high/low temperatures, andan unloader section 400 where the tested ICs which have been carried onthe test tray TST out of the chamber section 100 subsequently toundergoing a test in the testing chamber 100 are transferred from thetest tray TST to one or more general-purpose trays KST to be reloaded onthe latter. The unloader section 400 is generally constructed to sortout the tested ICs by categories on the basis of the data of the testresults and load them on the corresponding general-purpose trays.

[0009] The chamber section 100 comprises a constant temperature orthermostatic chamber 101 for receiving the ICs to be tested loaded onthe test tray TST and imposing an intended high or low temperaturestress to the ICs, a test or testing chamber 102 for effecting anelectrical test on the ICs subjected to the temperature stress in theconstant temperature chamber 101, and a temperature-stress removingchamber 103 for removing the temperature stress of the ICs having beenapplied thereto in the test chamber 102 from the ICs. The test chamber102 contains therein a tester head 104 of the testing apparatus,supplies various electric signals for testing via the tester head 104 tothe ICs to be tested in electrically contact therewith, receivesresponse signals from the ICs, and sends them to the testing apparatus.

[0010] Each of the test trays TST is moved in a circulating manner fromthe loader section 300 through the constant temperature chamber 101 ofthe chamber section 100, the test chamber 102 of the chamber section100, the temperature-stress removing chamber 103 of the chamber section100, and the unloader section 400 in this order, to the loader section300. The constant temperature chamber 101 and the temperature-stressremoving chamber 103 are taller than the test chamber 102, and haveupward portions protruding beyond the top of the test chamber 102,respectively. As shown in FIG. 5, a base plate 105 spans between theupward protruding portions of the constant temperature chamber 101 andthe temperature-stress removing chamber 103, and a test tray conveyingmeans 108 is mounted on the base plate 105 to transport the test trayTST from the temperature-stress removing chamber 103 to the constanttemperature chamber 101.

[0011] In case a temperature stress of a high temperature (a thermalstress) has been applied to the ICs to be tested in the constanttemperature chamber 101, the temperature-stress removing chamber 103cools the tested ICs down to room temperature by blowing, after whichthey are transported to the unloader section 400. On the other hand, incase a temperature stress of a low temperature such as, for instance,−30° C. (a cryogenic stress) has been applied to the Ics to be tested inthe constant temperature chamber 101, the temperature-stress removingchamber 103 heats the tested ICs by warm air or a heater up to atemperature at which the ICs have no any dew condensation, and then theyare carried out of the temperature-stress removing chamber 103 to theunloader section 400.

[0012] The test tray TST with the ICs loaded thereon in the loadersection 300 is conveyed from the loader section to the constanttemperature chamber 101 within the chamber section 100. The constanttemperature chamber 101 has a vertical conveyor means mounted thereinwhich is adapted to support a plurality of (nine, for instance) testtrays TST in the form of a stack. In the illustrated example, thevertical conveyor means stacks the transported test trays such that atest tray newly received from the loader section 300 is supported at theuppermost of the stack while the bottom test tray is delivered to thetest chamber 102. The ICs to be tested on the uppermost test tray TSTare given a predetermined high or low temperature stress while theassociated test tray TST is moved sequentially from the top to thebottom of the stack by vertically downward movement of the verticalconveyor means and/or waits till the immediately preceding test tray isbrought out of the test chamber 102. The tester head 104 is disposed inthe test chamber 102 at the central area thereof, and each of the testtrays TST carried out one by one from the constant temperature chamber101 is conveyed onto the tester head 104 while maintained at theconstant temperature, and a predetermined number of the ICs among theICs on the associated test tray TST are electrically connected to ICsockets (not shown) mounted on the tester head 104, as will be discussedhereinbelow. Upon completion of the test on all of the ICs placed on onetest tray TST through the tester head 104, the test tray TST istransported to the temperature-stress removing chamber 103 where thetested ICs on the associated test tray are relieved of temperaturestress to be restored to the ambient or room temperature, and thereafterthe test tray TST is discharged to the unloader section 400.

[0013] Like the constant temperature chamber 101 as described above, thetemperature-stress removing chamber 103 is also equipped with a verticalconveyor means adapted to support a plurality of (nine, for instance)test trays TST stacked one on another. In the illustrated example, thetest tray TST newly received from the test chamber 102 is supported atthe bottom of the stack while the uppermost test tray is discharged tothe unloader section 400. The tested ICs on the associated test tray arerelieved of temperature stress to be restored to the outside temperature(room temperature) as the associated test tray TST is moved from thebottom to the top of the stack by vertically upward movement of thevertical conveyor means.

[0014] The tested ICs as carried on the test tray TST are passed to theunloader section 400 where they are sorted out by categories based onthe test results and transferred from the test tray TST onto and storedin the corresponding general-purpose trays for respective categories.The test tray TST thus emptied in the unloader section 400 istransported to the loader section 300 where it is again loaded with ICsto be tested from a general-purpose tray KST onto the test tray TST,after which the same steps of above-described operation are repeated.

[0015] As shown in FIG. 5, an IC transfer means for transferring ICsfrom a general-purpose tray KST to a test tray TST in the loader section300 may be in the form of X and Y direction transfer means 304 whichcomprises a pair of spaced parallel rails 301 mounted on the base plate105 and extending over the loader section 400 in the front-to-back orforward-rearward direction of the testing apparatus (referred to as theY direction herein), a movable arm 302 which spans between the two rails301 and has its opposite ends secured thereto in a manner to be movablein the Y direction, and a movable head 303 which is supported by themovable arm 302 in a manner to be movable in the direction in which themovable arm 302 extends, that is. in the left to right direction of thetesting apparatus (referred to as the X direction herein). With thisarrangement, the movable head 303 is allowed to reciprocate between thetest tray TST and the general-purpose tray KST in the Y direction andmove along the movable arm 302 in the X direction.

[0016] On the underside of the movable head 303 are vertically movablymounted IC suction pads. Through the movement of the movable head 303 inthe X and Y directions and the downward movement of the suction pads incombination, the suction pads are brought into abutment with the ICsplaced on the general-purpose tray KST and pick them up and hold theretoby vacuum suction to transfer them to the test tray TST. The number ofsuction pads that are mounted on the movable head 303 may be eight, forinstance, so that a total of eight ICs may be transferred from thegeneral-purpose tray KST to the test tray TST at one time.

[0017] It is to be noted here that means 305 for correcting the positionof an IC called “preciser” (FIG. 5) is located between stoppingpositions for the general-purpose tray KST and the test tray TST. Theposition correcting means 305 includes relatively deep recesses intowhich the ICs as being attracted against the suction pads are oncereleased to fall prior to being transferred to the test tray TST. Therecesses are each defined by vertical tapered side walls which prescribefor the positions at which the ICs drop into the recesses by virtue ofthe tapering. After eight ICs have been precisely positioned relative toeach other by the position correcting means 305, those eight ICsaccurately positioned are again attracted against the suction pads andconveyed to the test tray TST. The reason that the position correctingmeans 305 is provided is as follows. Recesses of the general-purposetray TST for holding the ICs are sized larger as compared to the size ofICs, resulting in wide variations in positions of ICs placed on thegeneral-purpose tray KST. Consequently, if the ICs as such were vacuumpicked up by the suction pads and transferred directly to the test trayTST, there might be some of the ICs which could not be successfullydeposited into the IC storage recesses formed in the test tray TST. Thisis the reason for requiring the position correcting means 305, asdescribed above which acts to array ICs as accurately as the array ofthe IC storage recesses formed in the test tray TST.

[0018] The unloader section 400 is equipped with two sets of X and Ydirection transfer means 404 which are identical in construction to theX and Y direction transfer means 304 provided for the loader section300. The X and Y direction transfer means 404 perform to transship thetested ICs from the test tray TST delivered out to the unloader section400 onto the general-purpose tray KST. Each set of the X and Y directiontransfer means 404 comprises a pair of spaced parallel rails 401 mountedto extend in the forward-rearward direction of the testing apparatus (Ydirection), a movable arm 402 spanning between the pair of rails 401 andmovably mounted at opposite ends on the pair of rails 401 in the Ydirection, and a movable head 403 mounted on the movable arm 402 formovement therealong longitudinally of the arm, that is, in the right toleft direction of the testing apparatus (X direction).

[0019]FIG. 6 shows the construction of one example of the test tray TST.The illustrated test tray TST comprises a rectangular frame 12 having aplurality of equally spaced apart parallel cleats 13 between the opposedside frame members 12 a and 12 b of the frame, each of the cleats 13having a plurality of equally spaced apart mounting lugs 14 protrudingtherefrom on both sides thereof and each of the side frame members 12 a,12 b opposing the adjacent cleats having similar mounting lugs 14protruding therefrom. The mounting lugs 14 protruding from the opposedsides of each of the cleats 13 are arranged such that each of themounting lugs 14 protruding from one side of the cleat 13 is positionedintermediate two adjacent mounting lugs 14 protruding from the oppositeside of the cleat. Similarly, each of the mounting lugs 14 protrudingfrom each of the side frame members 12 a and 12 b is positionedintermediate two adjacent mounting lugs 14 protruding from the opposedcleat. Formed between each pair of opposed cleats 13 and between each ofthe side frame members 12 a and 12 b and the opposed cleats are spacesfor accommodating a multiplicity of IC carriers 16 in juxtaposition.More specifically, each IC carrier 16 is accommodated in one of an arrayof rectangular carrier compartments 15 defined in each of said spaces,each compartment 15 including two staggered, obliquely opposed mountinglugs 14 located at the diagonally opposed corners of the compartment. Inthe illustrated example wherein each cleat 13 has sixteen mounting lugs14 on either side thereof, there are sixteen carrier compartments 15formed in each of said spaces, in which sixteen IC carriers 16 aremounted. Since there are four of the spaces, 16×4, that is, 64 ICcarriers in total can be mounted in one test tray TST. Each IC carrier16 is placed on corresponding two mounting lugs 14 and fixed thereto byfasteners 17.

[0020] Each of IC carriers 16 is of identical shape and size in itsouter contour and has an IC pocket 19 in the center for accommodating anIC element therein. The shape and size of the IC pocket 19 is determineddepending on those of the IC element 18 to be accommodated therein. Inthe illustrated example, the IC pocket 19 is in the shape of a generallysquare recess. The outer dimensions of the IC pocket 19 are sized so asto be loosely fitted in the space defined between the opposed mountinglugs 14 in the carrier compartment 15. The IC carrier 16 has flanges atits opposed ends adapted to rest on the corresponding mounting lugs 14,these flanges having mounting holes 21 and holes 22 formed therethrough,respectively, the mounting holes 21 being adapted to receive fasteners17 therethrough and the holes 22 being adapted to pass locating pinstherethrough.

[0021] In order to prevent IC elements from slipping out of place withinthe IC carrier 16 or jumping out of the IC carrier 16, a pair of latches23 are attached to the IC carrier 16, as shown in FIG. 7. These latches23 are integrally formed with the body of the IC carrier so as to extendupwardly from the base of the IC pocket 19, and are normally resilientlybiased such that the top end pawls are urged toward each other by virtueof the resiliency of the resin material of which the IC carrier is made.When the IC element is to be deposited into or removed from the ICpocket 19, the top ends of the two latches 23 are expanded away fromeach other by a latch releasing mechanism 25 disposed on opposite sidesof an IC suction pad 24 for picking up an IC element prior toeffectuating the deposition of the IC element into or removal from theIC pocket 19. Upon the latch releasing mechanism 25 being moved out ofengagement with the latches 23, the latches 23 will snap back to theirnormal positions by their resilient forces where the deposited IC isheld in place against dislodgement by the top end pawls of the latches23.

[0022] The IC carrier 16 holds an IC element in place with its leads orpins 18 exposed downwardly as shown in FIG. 8. The tester head 104 hasan IC socket mounted thereto, and contacts 26 of the IC socket upwardlyextend from the top surface of the tester head 104. The exposed leads 18of the IC element are pushed against the contacts 26 of the IC socket toestablish electrical connection between the IC element and the socket.To this end, a pusher 20 for pushing and holding an IC element down ismounted above the tester head 104 and is configured to push the ICelement accommodated in an IC carrier 16 from above into contact withthe tester head 104.

[0023] The number of IC elements which may be connected with the testerhead 104 at a time depends on the number of IC sockets mounted on thetester head 104. By way of example, where sixty-four IC elements arearranged in an array of 4 lines×16 rows on a test tray TST as shown inFIG. 9, 4×4, that is, 16 IC sockets are arranged and mounted on thetester head 104 such that the IC elements (shown as obliquely hatched)in every fourth row in each of the lines may be tested all at one time.More specifically, in the first test run the examination is conducted onsixteen IC elements located in the first, fifth, ninth and thirteenthrows in each line, the second test run is effected on another sixteen ICelements located in the second, sixth, tenth and fourteenth rows in eachline by shifting the test tray TST by a distance corresponding to onerow of IC elements, and the third and fourth test runs are carried outin the similar manner until all of the IC elements are tested. The testresults are stored in a memory at the addresses determined by, forinstance, serial numbers (serial numbers in one lot or batch) assignedto ICs, the identification number given to the test tray TST and thenumbers assigned to the IC pockets in the test tray. It is to beappreciated that where thirty-two IC sockets may be mounted on thetester head 104, only two test runs are required to examine allsixty-four IC elements arranged in an array of 4 lines×16 rows. It isalso to be noted that there is another type of IC handler in which ICsto be tested are transferred from the test tray into a socket mounted onthe tester head 104 and upon the test being completed the tested ICs aretransferred from the socket back onto the test tray to transport theICs, in the test chamber 102.

[0024] The IC storage section 200 comprises an IC storage rack (orstocker) 201 for accommodating general-purpose trays KST loaded with ICsto be tested and a tested IC storage rack (or stocker) 202 foraccommodating general-purpose trays KST loaded with tested ICs sortedout by categories on the basis of the test results. The IC storage rack201 and tested IC storage rack 202 are configured to accommodategeneral-purpose trays in the form of a stack. The general-purpose traysKST with ICs to be tested carried thereon and stored in the form of astack in the IC storage rack 201 are transported successively from thetop of the stack to the loader section 300 where the ICs to be tested(DUTS) are transferred from the general-purpose tray KST onto a testtray TST on standby in the loader section 300.

[0025] Each of the IC storage rack 201 and the tested IC storage rack202 may be of identical shape and structure. Either of the IC storagerack 201 and any one of the tested IC storage racks 202 comprises, asany one of the IC storage rack 201 and the tested IC storage racks 202is shown in FIG. 10, a tray supporting frame 203 open at the top andhaving an opening at the bottom, and an elevator 204 disposed below theframe 203 so as to be vertically movable through the bottom opening. Inthe tray supporting frame 203 there are stored and supported a pluralityof general-purpose trays KST stacked one on another which are verticallymoved by the elevator 204 acting through the bottom opening of the frame203.

[0026] In the example illustrated in FIGS. 4 and 5, eight racks STK-1,STK-2, . . . , STK-8 are provided as tested IC storage racks 202 so asto be able to store tested ICs which may be sorted out into eightcategories at a maximum according to the test results. This is becausein some applications tested ICs may not only be classified intocategories of “conformable or pass article” and “unconformable orfailure article” but also be subclassified into those having high,medium and low operation speeds among the “pass” articles and thoserequired to be retested among the “failure” articles, and others. Evenif the number of classifiable categories is up to eight, the unloadersection 400 in the illustrated example is capable of accommodating onlyfour general-purpose trays KST. For this reason, if there occur someamong the tested ICs which should be classified into a category otherthan categories assigned to the general-purpose trays KST arranged inthe unloader section 400, the procedures taken are to return one of thegeneral-purpose trays KST from the unloader section 400 to the ICstorage section 200 and in replacement to transfer a general-purposetray KST for storing the ICs belonging to the new additional categoryfrom the IC storage section 200 to the unloader section 400 where thoseICs are stored in the new tray.

[0027] Referring to FIG. 5, a tray transfer means 205 is disposed abovethe IC storage rack 201 and the tested IC storage racks 202 for movementover the entire extent of the storage racks 201 and 202 in the directionof arrangement of the racks (in the right to left direction of thetesting apparatus) relative to the base plate 105. The tray transfermeans 205 is provided on its bottom with grasp means for grasping ageneral-purpose tray KST. The tray transfer means 205 is moved to aposition over the IC storage rack 201 whereupon the elevator 204 isactuated to lift the general-purpose trays KST stacked in the IC storagerack 201, so that the uppermost general-purpose tray KST may be pickedup by the grasp means of the tray transfer means 205. Once the uppermostgeneral-purpose tray KST loaded with ICs to be tested has beentransferred to the tray transfer means 205, the elevator 204 is loweredto its original position. The tray transfer means 205 is thenhorizontally moved to and stopped at a predetermined position in theloader section 300 where the grasp means of the tray transfer means 205is released to allow the general-purpose tray KST to drop into animmediately underlying tray receiver (not shown). The tray transfermeans 205 from which the general-purpose tray KST has been unloaded ismoved out of the loader section 300. Then, the elevator 204 is movedupward from below the tray receiver having the general-purpose tray KSTdeposited thereon to lift up the tray receiver and hence thegeneral-purpose tray KST loaded with ICs to be tested so that thegeneral-purpose tray KST is kept exposed up through a window 106 formedin the base plate 105.

[0028] The base plate 105 is formed in the area overlying the unloadersection 400 with another two similar windows 106 through which emptygeneral-purpose trays are kept exposed. In this example, each of thewindows 106 is sized to expose two general-purpose trays therethrough.Hence, four empty general-purpose trays are kept exposed up through twowindows 106. Tested ICs are sorted out and stored in these emptygeneral-purpose trays KST according to the categories assigned torespective trays. As with the loader section 300, the four emptygeneral-purpose trays KST are placed on the respective tray receiverswhich are moved up and down by the associated elevators 204. Once onegeneral-purpose tray KST has been fully filled, the tray is lowered fromthe level of the window 16 by the elevator 204 and stored in the traystorage position assigned to said tray by the tray transfer means 205.Indicated by the numeral 206 in FIGS. 4 and 5 is an empty tray storagerack for accommodating empty general-purpose trays KST. From this emptytray storage rack 206, empty general-purpose trays are transported tothe respective windows 106 by the tray transfer means 205 and theelevators 204 and held thereat by the associated elevators 204 to beready for receiving tested ICs.

[0029] As described above, in an IC testing apparatus having a handlerof the foregoing type (2) mounted thereto in which ICs to be tested aretransferred onto a test tray and transported to the test section(chamber section) to perform a test, it is possible to reduce a timerequired to test all the ICs because the number of ICs undergoing a testat a time can be increased. On the other hand, in the unloader sectionit takes a considerable time to carry out the transfer operation of thetested ICs since only ICs of eight or so are sorted out and transferredfrom a test tray onto a general-purpose tray at a time. Moreover, thetransfer operation of the tested ICs in the unloader section accompaniesthe sorting operation of the tested ICs which takes a considerable time.To this end, though two sets of X and Y direction transfer means areprovided in the unloader section 400, there still occurs a disadvantagethat a time needed to sort out the tested ICs is longer than a timerequired to test all the ICs.

[0030] In addition, in an IC testing apparatus having a handler of theforegoing type (2) mounted thereto, in transferring the tested ICs froma test tray TST onto a general-purpose tray KST in the unloader section400, the X and Y direction transfer means 404 stores in a storage devicethe facts that the tested ICs on the test tray have been transferredonto general-purpose trays by storing the addresses assigned to therespective IC carriers 16 on the associated test tray TST, and itperforms the transfer operation of the tested ICs onto general-purposetrays on the basis of the stored addresses so as not to remain anytested IC or ICs which have failed to transfer on the test tray TST.However, there is a rare case that the tested IC or ICs remain on thetest tray without being transferred therefrom.

[0031] If one or more tested ICs should not have been transferred andhave remained on the test tray TST in the unloader section 400, the testtray TST loaded with one or more ICs not transferred is transported tothe loader section 300, and hence an IC or ICs to be tested are loadedon the remaining tested IC or ICs in the form of a stack. In such case,the IC to be tested positioned at the upper side of the stack protrudesupwardly from the upper surface of the test tray. Therefore, thereoccurs a disadvantage that when the test tray loaded with the stack orstacks each of two ICs is transported to the constant temperaturechamber 101 and then the subsequent test tray is stacked on the testtray with the stack or stacks of two ICs in the constant temperaturechamber 101, the IC to be tested positioned at the upper side of thestack and protruding upwardly is pushed out of the associated test trayby insertion of the subsequent test tray and dropped down therefrom oran accident such as breakage of the IC to be tested may happen.

[0032] If an accident occurs that an IC drops down out of the associatedtest tray TST in the constant temperature chamber 101, it may occur thatthe IC drops down on a carrying mechanism or the like provided on thelower side of the constant temperature chamber 101 and interferestherewith so that the carrying mechanism can fail to convey. Inaddition, if the IC to be tested as being stacked on the remainingtested IC should be tested and transported to the unloader section 400without dropping out of the test tray, the upper IC in the stack issorted out on the basis of the test results of the lower remainingtested IC in the stack, and hence there is a disadvantage that anerroneous classification is done.

SUMMARY OF THE INVENTION

[0033] It is therefore an object of the present invention to provide anIC testing system which can carry out at high speed the transferoperation of the tested ICs from a test tray to a general-purpose trayin the unloader section.

[0034] A second object of the present invention is to provide an ICtesting system having a plurality of IC testing apparatus in which testsof different conditions can sequentially be carried out on a largenumber of ICs using the plurality of IC testing apparatus, and in whichplural test runs to be performed on a large number of ICs can be allexecuted within a time interval as short as possible and the sortingoperation of the tested ICs based on the test results thereof can alsobe performed in a short time.

[0035] A third object of the present invention is to provide an ICtesting apparatus which is able to prevent from occurring an accidentthat one or more tested ICs are left on a test tray without beingtransferred therefrom.

[0036] A fourth object of the present invention is to provide an ICtesting apparatus which ia capable of detecting that one or more ICshave been dropped out from the associated test tray loaded with ICsthereon.

[0037] According to a first aspect of the present invention, there isprovided an IC testing system including an IC testing apparatus which isarranged such that ICs to be tested are transferred from ageneral-purpose tray onto a test tray to be reloaded thereon in a loadersection, the test tray with the ICs loaded thereon is transportedthrough a constant temperature or thermostatic chamber into a test ortesting section where the ICs loaded on the test tray are caused toundergo a test, and after the completion of the test, the test tray withthe tested ICs loaded thereon is transported to an unloader sectionwhere the tested ICs are transferred from the test tray onto ageneral-purpose tray, and further comprising a dedicated classifyingmachine for exclusively performing the sorting operation of the testedICs loaded on the general-purpose tray, and storage information memorymeans provided in a host computer for controlling the IC testingapparatus or in the IC testing apparatus. Storage information such asthe test results of each tested IC stored in corresponding one ICreceiving portion of the general-purpose tray, the number of a socketwith which the IC has been brought into contact in the test section, andthe like is stored in the storage information memory means at an addressthereof which is determined by a serial number assigned to each IC, anidentification number assigned to each general-purpose tray, and thenumber assigned to each of IC receiving portions of each general-purposetray, and the classifying operation of the tested Ics is done on thebasis of the storage information using the dedicated classifyingmachine.

[0038] With the IC testing system according to the first aspect of theinvention, it is possible that all the tested ICs can be sorted by thededicated classifying machine utilizing the storage information storedin the storage information memory means. Accordingly, since there is noneed for carrying out the classifying operation of the tested ICs andonly the transfer operation of the ICs from the test tray to thegeneral-purpose tray is required in the unloader section, the transferoperation of the ICs can be done at high speed. In particular, in casethere is not disposed in the unloader section a general-purpose traycorresponding to the category into which the tested IC is to be sorted,because of many categories into which the tested ICs are to be sorted,it is unnecessary to transport a general-purpose tray for thecorresponding category to the unloader section, and hence the processingspeed can be improved.

[0039] According to a second aspect of the present invention, there isprovided an IC testing system including a plurality of IC testingapparatus each of which is arranged such that ICs to be tested aretransferred from a general-purpose tray onto a test tray to be reloadedthereon in a loader section, the test tray with the ICs loaded thereonis transported through a constant temperature or thermostatic chamberinto a test section where the ICs loaded on the test tray are caused toundergo a test, and after the completion of the test, the test tray withthe tested ICs loaded thereon is transported to an unloader sectionwhere the tested ICs are transferred from the test tray onto ageneral-purpose tray, and further comprising a dedicated classifyingmachine for exclusively performing the sorting operation of the testedICs loaded on the general-purpose tray, and storage information memorymeans provided in a host computer for controlling the plurality of ICtesting apparatus or in each IC testing apparatus. Storage informationsuch as the test results of each IC stored in corresponding one ICreceiving portion of the general-purpose tray, the number of a socketwith which the IC has been brought into contact in the test section, andthe like is stored in the storage information memory means at an addressthereof which is determined by a serial number assigned to each IC, anidentification number assigned to each general-purpose tray, and thenumber assigned to each of the IC receiving portions of eachgeneral-purpose tray. Each IC testing apparatus sorts out the tested ICsinto only two categories of the conformable or pass ICs and theunconformable or failure ICs, and the dedicated classifying machineexecutes the sub-classifying operation of the tested ICs on the basis ofthe storage information stored in the storage information memory means.

[0040] In the IC testing system according to the second aspect of theinvention, since the classifying operation of the tested ICs in theunloader section is limited to only choose between the two, the transferoperation of the ICs from the test tray to the general-purpose tray inthe unloader section can be carried out at higher speed than the casethat the tested ICs are sorted out into all the categories in theunloader section. In addition, since the ICs which have been oncedetermined to be failure ICs are not transported to the subsequent ICtesting apparatus for testing under next test condition, the failure ICscannot be tested again and the testing time can be reduced. Therefore,there is an advantage that ICs can be tested at high speed. Moreover,the tested ICs are further sorted out into sub-categories by thededicated classifying machine utilizing the storage information storedin the storage information memory means, and hence in case there is notdisposed in the unloader section a general-purpose tray corresponding tothe category into which the tested IC is to be sorted, it is unnecessaryto transport a general-purpose tray for the corresponding category tothe unloader section. Accordingly, the processing speed can beincreased.

[0041] According to a third aspect of the present invention, there isprovided an IC testing apparatus which is arranged such that ICs to betested are transferred from a general-purpose tray to a test tray to bereloaded thereon in a loader section, and the test tray loaded with theICs is transported into a test section where the ICs undergo a test,after the completion of the test, the test tray loaded with the testedICs is transported from the test section to an unloader section wherethe tested ICs on the test tray are transferred from the associated testtray onto a general-purpose tray, and the test tray which has beenemptied of the tested ICs is transported from the unloader section tothe loader section where new ICs to be tested are loaded on the emptiedtest tray for successively testing ICs, and comprises an IC detectingsensor for detecting whether an IC exists on the test tray beingtransported or not, the IC detecting sensor being provided between theunloader section and the loader section so that the presence of any IChaving been left on the test tray can be detected.

[0042] According to a fourth aspect of the present invention, there isprovided an IC testing apparatus which is arranged such that ICs to betested are transferred from a general-purpose tray to a test tray to bereloaded thereon in a loader section, and the test tray loaded with theICs is transported into a test section where the ICs undergo a test,after the completion of the test, the test tray loaded with the testedICs is transported from the test section to an unloader section wherethe tested ICs on the test tray are transferred from the associated testtray onto a general-purpose tray, and the test tray which has beenemptied of the tested ICs is transported from the unloader section tothe loader section where new ICs to be tested are loaded on the emptiedtest tray for successively testing ICs, and comprises an IC detectingsensor for detecting whether an emptied IC receiving portion having noIC therein exists in the test tray or not, the IC detecting sensor beingprovided on the way of the carrying path of the test tray transportedfrom the test section to the unloader section.

[0043] According to a fifth aspect of the present invention, there isprovided an IC testing apparatus which is arranged such that ICs to betested are transferred from a general-purpose tray to a test tray to bereloaded thereon in a loader section, and the test tray loaded with theICs is transported into a test section where the ICs undergo a test,after the completion of the test, the test tray loaded with the testedICs is transported from the test section to an unloader section wherethe tested ICs on the test tray are transferred from the associated testtray onto a general-purpose tray, and the test tray which has beenemptied of the tested ICs is transported from the unloader section tothe loader section where new ICs to be tested are loaded on the emptiedtest tray for successively testing ICs, and comprises an IC detectingsensor for detecting whether an emptied IC receiving portion having noIC therein exists in the test tray or not, the IC detecting sensor beingprovided on the way of the carrying path of the test tray transportedfrom the loader section to the test section.

[0044] In the IC testing apparatus of the third aspect of the invention,even if an IC should have been left on the test tray being transportedfrom the unloader section to the loader section, the presence of that ICremaining on the test tray can be detected, and hence, when the testtray arrives at the loader section, the remaining IC on the test traycan be removed from the test tray. As a result, there occurs no accidentthat two ICs are stacked one on another and the upper side IC of thestack is dropped down on the bottom of the constant temperature chamber.Accordingly, an IC testing apparatus having high safety can be provided.

[0045] In the IC testing apparatus of the fourth aspect of theinvention, even if any tested IC should drop down out of the test trayin the test section, the position of the IC receiving portion of thetest tray from which the IC has been dropped down can be detected duringthe transportation time of the test tray from the test section to theunloader section. Therefore, it is possible in the unloader section tostop a classifying operation for the IC receiving portion where no ICexists and the time required for the classifying operation can bereduced.

[0046] In the IC testing apparatus of the fifth aspect of the invention,even if any IC should drop down out of the test tray during thetransportation time of the test tray from the loader section to the testsection, the emptied IC receiving portion of the test tray from whichthe IC has been dropped down can be detected until the test tray arrivesat the test section. Therefore, it is possible in the test section tostop a testing operation for the IC receiving portion where no IC existsand the time required for the testing operation can be reduced since nowaste of time is expended.

BRIEF DESCRIPTION OF THE DRAWINGS

[0047]FIG. 1 is a block diagram showing the whole construction of afirst embodiment of the IC testing system according to the presentinvention;

[0048]FIG. 2 is a perspective view schematically illustrating an exampleof the container which can convey a set of plural general-purpose traysand can be used in the IC testing system shown in FIG. 1;

[0049]FIG. 3 is a block diagram showing the whole construction of asecond embodiment of the IC testing system according to the presentinvention;

[0050]FIG. 4 is a plan view schematically showing a conventional ICtesting apparatus with the chamber section viewed in perspective;

[0051]FIG. 5 is a perspective view of the conventional IC testingapparatus shown in FIG. 4;

[0052]FIG. 6 is an exploded perspective view explaining the structure ofan example of a test tray for use in the IC testing apparatus;

[0053]FIG. 7 is a perspective view explaining how ICs are loaded on thetest tray depicted in FIG. 6;

[0054]FIG. 8 is an enlarged sectional view illustrating an electricalconnection between an IC loaded on the test tray shown in FIG. 6 and atester head;

[0055]FIG. 9 is a plan view explaining a sequence of steps of testingthe ICs to be tested loaded on the test tray;

[0056]FIG. 10 is a perspective view illustrating the structure of a rackfor storing general-purpose trays for use in the IC testing apparatus;

[0057]FIG. 11 is a perspective view showing a construction of the mainportion of an embodiment of the IC testing apparatus according to thepresent invention;

[0058]FIG. 12 is a generally sectional view of FIG. 11; and

[0059]FIG. 13 is an enlarged perspective view showing a portion of theIC testing apparatus shown in FIG. 11.

BEST MODE FOR CARRYING OUT THE INVENTION

[0060]FIG. 1 shows a first embodiment of the IC testing system accordingto the present invention. This IC testing system comprises three ICtesting apparatus 1A, 1B and 1C. Each of the IC testing apparatus 1A, 1Band 1C has the same construction or configuration and comprises anelectrical portion, i.e., an IC tester part 10 (principally the lowerelectrical portion in FIG. 5) of the IC testing apparatus for measuringthe electrical characteristics of ICs under test by applying testsignals of a predetermined pattern to the ICs, and a handler part 11(principally the upper mechanical portion in FIG. 5). The IC tester part10 of each IC testing apparatus is under control of a host computer 2and is controlled by this host computer 2. In addition, a dedicatedclassifying machine 3 for exclusively executing classification of testedICs is provided. Further, it is often customary to incorporate twohandler parts 11 with respect to the single IC tester part 10 so thatthe combination of the two handler parts and the single IC tester partmay be operated as one IC tester apparatus. Although not shown, each ofthe IC testing apparatus in this embodiment is also arranged such thattwo handler parts 11 are mounted to single IC tester part.

[0061] As with the conventional IC testing apparatus described abovewith reference to FIGS. 4 to 10, the handler part 11 of each IC testingapparatus 1A, 1B or 1C comprises a chamber section for testing ICs whichhave been carried on a test tray, an IC storage section for storing ICsto be tested and ICs already tested and sorted out, a loader sectionwhere ICs to be tested which a user has beforehand loaded ongeneral-purpose trays are transferred and reloaded onto a test traycapable of withstanding high/low temperatures, and an unloader sectionwhere the tested ICs which have been carried on the test tray out of thechamber section subsequently to undergoing a test therein aretransferred from the test tray to the general-purpose trays to bereloaded on the latter. The chamber section comprises a constanttemperature chamber for imposing a temperature stress of either adesigned high or low temperature on ICs to be tested loaded on a testtray, a test chamber for conducting electrical tests on the ICs underthe temperature stress imposed in the constant temperature chamber bybringing the ICs into electrical contact with a tester head of the ICtester part 10, and a temperature-stress removing chamber for removingthe temperature stress imposed in the constant temperature chamber fromthe ICs having undergone the tests in the test chamber.

[0062] In this embodiment, each of the IC testing apparatus 1A, 1B and1C is characterized in that each IC testing apparatus tests ICs underthe same test condition and the tested ICs are transferred from the testtray to the general-purpose trays without sorting out the tested ICs inthe unloader section of each handler part 11, and after plural test runshave been all completed, the tested ICs are transported to the dedicatedclassifying machine 3 wherein the classifying operation of the testedICs is executed in a lump.

[0063] To this end, in this embodiment, storage information memory means4 is provided in the host computer 2. All the test results of the ICsare stored in the storage information memory means 4. The test resultsof the ICs are stored at respective addresses of the storage informationmemory means 4, each address of which is determined by a serial numberassigned to each IC, an identification number given to eachgeneral-purpose tray, a number allocated to each of IC pockets of eachgeneral-purpose tray in the correspondence thereto, and the like everytime one of the tested ICs is transferred from the test tray to thegeneral-purpose tray in the unloader section of each handler part 11.Examples of the test results include the condition of the tests, aclassification of the tested ICs by operation speeds such as “highspeed”, “medium speed” and “low speed” among the pass ICs, the presenceof those required to be retested among the failure ICs, the number ofthe socket of the tester head with which each IC was brought into ontesting, and others. The storage information to be stored is transmittedto the host computer 2 via the IC tester part 10 by means ofcommunication means 5 such as, for example, a GPIB communication portbetween computers or an RS232C communication port or the like to bestored in the storage information memory means 4.

[0064] The storage information memory means 4 may be composed of amemory. The storage information stored in the storage information memorymeans 4 may be supplied to the dedicated classifying machine 3, forexample, by storing the information in a storage medium such as a floppydisk separately for each of the IC testing apparatus 1A, 1B and IC, ormay be transferred to the dedicated classifying machine 3 utilizing thecommunication means 5.

[0065] The general-purpose trays each loaded with the tested ICs whichhave been transferred without having been sorted out in the unloadersection of each handler part 11 may be transported to the dedicatedclassifying machine 3 by accommodating the trays, for example, in abox-shaped container 27 in which shelves for receiving a plurality ofthe general-purpose trays KST in horizontal positions (levels) areprovided as shown in FIG. 2, or may be transported to the dedicatedclassifying machine 3 by a tray transfer apparatus installed to spanbetween each handler part 11 and the dedicated classifying machine 3.The container 27 has an opening and shutting lid 28 for taking thegeneral-purpose trays KST therein and thereout. The dedicatedclassifying machine 3 has an IC suction head provided therein, whichpicks up an IC from a general-purpose tray KST transported to theclassifying machine 3, and executes a sorting operation of the tested ICin accordance with the storage information stored at an addresscorresponding to the position of the general-purpose tray KST from whichthe IC has been picked up by the IC suction head.

[0066]FIG. 3 shows a second embodiment of the IC testing systemaccording to the present invention. The IC testing system of this secondembodiment also comprises three IC testing apparatus 1A, 1B and 1C aswith the aforementioned IC testing system of the first embodiment. Eachof the IC testing apparatus 1A, 1B and 1C has the same construction orconfiguration and comprises an IC tester part 10 which is an electricalportion of the IC testing apparatus for measuring the electricalcharacteristics of Ics under test by applying test signals of apredetermined pattern to the ICs, and a handler part 11. The IC testerpart 10 of each IC testing apparatus is under control of a host computer2 and is controlled by this host computer 2. In addition, a dedicatedclassifying machine 3 for exclusively executing classification of testedICs is provided. Further, each of the IC testing apparatus in thisembodiment is also arranged such that two handler parts 11 are mountedto single IC tester part.

[0067] Like the conventional IC testing apparatus described above withreference to FIGS. 4 to 10, the handler part 11 of each IC testingapparatus 1A, 1B or IC comprises a chamber section for testing ICs whichhave been carried on a test tray, an IC storage section for storing ICsto be tested and ICs already tested and sorted out, a loader sectionwhere ICs to be tested which a user has beforehand loaded ongeneral-purpose trays are transferred and reloaded onto a test traycapable of withstanding high/low temperatures, and an unloader sectionwhere the tested ICs which have been carried on the test tray out of thechamber section subsequently to undergoing a test therein aretransferred from the test tray to the general-purpose trays to bereloaded on the latter. The chamber section comprises a constanttemperature chamber for imposing a temperature stress of either adesigned high or low temperature on ICs to be tested loaded on a testtray, a test chamber for conducting electrical tests on the ICs underthe temperature stress imposed in the constant temperature chamber bybringing the ICs into electrical contact with a tester head of the ICtester part 10, and a temperature-stress removing chamber for removingthe temperature stress imposed in the constant temperature chamber fromthe ICs having undergone the tests in the test chamber.

[0068] In the second embodiment, each of the IC testing apparatus 1A, 1Band 1C performs a test of ICs under a different test condition from oneother. Examples of the test conditions include, for instance, differenttemperatures imposed on ICs to be tested or different operation voltagesapplied to ICs under test or the like. In addition, storage informationmemory means 4 is provided in the host computer 2.

[0069] First, all the ICs under test are tested in the first stage ICtesting apparatus 1A. The ICs under test are loaded on one or moregeneral-purpose trays and are transported with the general-purpose traysto the handler part 11 of the IC testing apparatus 1A. A plurality ofthe general-purpose trays are accommodated in, for example, atransporting container 27 as described above with reference to FIG. 2 inthe form of a stack. The container 27 is mounted to the handler part 11of the IC testing apparatus 1A with the lid 28 opened. Thegeneral-purpose trays KST are conveyed out of the container 27 one byone and are carried to the loader section. In the loader section, theICs loaded on a general-purpose tray KST are transferred to a test traywhich is transported to the test chamber via the constant temperaturechamber. In the test chamber the ICs are electrically contacted to thetester head of the IC tester part 10 located in the test chamber to testthe electrical characteristics of the ICs. When the test for all of theICs loaded on the test tray is completed, the test tray is conveyed outof the test chamber to the temperature stress removing chamber where thetested ICs on the associated test tray are relieved oftemperature-stress and thereafter the test tray is discharged to theunloader section.

[0070] The tested ICs on the test tray are transferred to ageneral-purpose tray KST in the unloader section. In case this transferoperation is performed, in this second embodiment, at least two emptygeneral-purpose trays KST are transported to the unloader section andthe tested ICs are sorted out into only pass ICs and failure ICs whichare to be loaded separately on the empty general-purpose trays KST. Whena general-purpose tray KST is filled up with pass ICs or failure ICs,the filled general-purpose tray KST is carried back into the container27 by transporting means. In the container 27, the general-purpose traysKST each having the failure ICs loaded thereon are received, forinstance, in the lower side shelves in order from the lowermost shelfsuch that the first general-purpose tray KST loaded with the failure ICsis received in the lowermost shelf, the second general-purpose tray KSTloaded with the failure ICs is received in the second lowermost shelf,and so on. On the other hand, the general-purpose trays KST each havingthe pass ICs loaded thereon are received, for instance, in the upperside shelves in order from the uppermost shelf such that the firstgeneral-purpose tray KST loaded with the pass ICs is received in theuppermost shelf, the second general purpose tray KST loaded with thepass ICs is received in the second uppermost shelf, and so on. In such away, the general-purpose trays each loaded with the pass ICs and thegeneral-purpose trays each loaded with the failure ICs are classified inthe container 27.

[0071] When the test in the first stage IC testing apparatus 1A iscompleted, the container 27 accommodating the general-purpose trays KSTon which the tested ICs are loaded as described above is moved to thesecond stage IC testing apparatus 1B. This second stage IC testingapparatus 1B performs a test under the condition which is different fromthat in the first stage IC testing apparatus 1A. In the second stage ICtesting apparatus 1B, however, only the general-purpose trays loadedwith the tested pass ICs are taken out of the container 27 and areconveyed to the loader section where only the ICs as determined to bepass ICs will be tested. As a result of the test executed in the secondIC testing apparatus 1B, namely, the second test run, when one or moreICs are determined to be failure ICs, a general-purpose tray loaded withthe failure ICs and accommodated in the container 27 (a tray havingempty IC pockets therein) is transported to the unloader section wherethe tested ICs as determined to be failure ICs in the second stage ICtesting apparatus 1B are transferred from the test tray to thatgeneral-purpose tray. In case any of the general-purpose trays eachloaded with the failure ICs and accommodated in the container 27 has noempty IC pocket therein, an empty general-purpose tray is transported tothe unloader section from the container 27 or from an empty tray storagerack.

[0072] When all of the tested ICs as determined to be pass ICs in thefirst stage IC testing apparatus 1A are tested in the second stage ICtesting apparatus 1B, and the general-purpose trays loaded with the passICs and the general-purpose trays loaded with the failure ICs arereceived in the container 27, the container 27 is moved to the thirdstage IC testing apparatus 1C. This third stage IC testing apparatus 1Cexecutes a test under the condition which is further different fromthose in the first and second stage IC testing apparatus 1A and 1B. Aswith the immediately preceding IC testing apparatus 1B, only thegeneral-purpose trays loaded with the tested pass ICs are taken out ofthe container 27 and are conveyed to the loader section where only theICs as determined to be pass ICs will be tested in the third stage (laststage) IC testing apparatus 1C. The last stage IC testing apparatus 1Ctransmits the test results to the host computer 2 for each IC loaded oneach general-purpose tray, and the transmitted test results are storedin the storage information memory means 4 provided in the host computer2.

[0073] As a result of the test executed in the last stage IC testingapparatus 1C, namely, the third test run, when one or more ICs aredetermined to be failure ICs, a general-purpose tray loaded with thefailure ICs and accommodated in the container 27 (a tray having empty ICpockets therein) is transported to the unloader section where the testedICs as determined to be failure ICs in the last stage IC testingapparatus 1C are transferred from the test tray to that general-purposetray. In case any of the general-purpose trays each loaded with thefailure ICs and accommodated in the container 27 has no empty IC pockettherein, an empty general-purpose tray is transported to the unloadersection from the container 27 or from an empty tray storage rack.

[0074] When all of the ICs as determined to be pass ICs in the precedingtwo test runs are tested in the last stage IC testing apparatus 1C, thecontainer 27 is moved from the last stage IC testing apparatus 1C to thededicated classifying machine 3. The dedicated classifying machine 3sorts out the tested ICs in the container 27 in accordance with thestorage information sent from the host computer 2. In this case, sincethe storage information sent from the host computer 2 is only theinformation on the tested ICs transmitted from the last stage IC testingapparatus 1C, the test results of the tested ICs as determined to befailure ICs in the first and second two test runs have not been-storedin the storage information memory means 4 of the host computer 2.Therefore, if it is desired to further subclassify the tested ICs asdetermined to be failure ICs in the first and second test runs, althoughit takes some time period to execute the sorting operation, the testresults of the tested ICs as determined to be failure ICs in the firstand second stage IC testing apparatus 1A and 1B may be transmitted fromthe IC testing apparatus 1A and 1B to the host computer 2 to be storedin the storage information memory means 4, and on completing all of thetests, the tested ICs as determined to be failure and received in thecontainer 27 may also be sorted out in subclasses in accordance with thestorage information transmitted from the host computer 2 using thededicated classifying machine 3.

[0075] Further, the examples that three IC testing apparatus IA, 1B and1C are provided have been described in the first and second embodimentsshown in FIGS. 1 and 3, respectively. However, there is no limitation onthe number of IC testing apparatus. In addition, only by a combinationof the IC testing apparatus 1C and the dedicated classifying machine 3,the processing speed in the handler part 11 can be increased.Accordingly, even by the combination of the IC testing apparatus 1C andthe dedicated classifying machine 3, the aforementioned object of thepresent invention can be achieved. Further, the IC testing system of thesecond embodiment can effectively be applied to an IC testing apparatushaving a handler of the type (1) mounted thereto as described in theprior art paragraph.

[0076]FIG. 11 shows an embodiment of the IC testing apparatus accordingto the present invention. This IC testing apparatus has a handler of theaforementioned type (2) mounted thereto, and comprises an IC tester part(principally the lower electrical portion in FIG. 5) which is anelectrical portion of the IC testing apparatus for measuring theelectrical characteristics of ICs under test by applying test signals ofa predetermined pattern to the ICs, and a handler part (principally theupper mechanical portion in FIG. 5). As with the conventional IC testingapparatus described above with reference to FIGS. 4 to 10, the handlerpart comprises a chamber section for testing ICs which have been carriedon a test tray, an IC storage section for storing ICs to be tested andICs already tested and sorted out, a loader section where ICS to betested which a user has beforehand loaded on general-purpose trays aretransferred and reloaded onto a test tray capable of withstandinghigh/low temperatures, and an unloader section where the tested ICswhich have been carried on the test tray out of the chamber sectionsubsequently to undergoing a test therein are transferred from the testtray to the general-purpose trays to be reloaded on the latter. Thechamber section comprises a constant temperature chamber for imposing atemperature stress of either a designed high or low temperature on ICsto be tested loaded on a test tray, a test chamber for conductingelectrical tests on the ICs under the temperature stress imposed in theconstant temperature chamber by bringing the ICs into electrical contactwith a tester head of the IC tester part, and a temperature-stressremoving chamber for removing the temperature stress imposed in theconstant temperature chamber from the ICs having undergone the tests inthe test chamber.

[0077]FIG. 11 is an illustration for explaining the construction of anessential portion of this embodiment wherein a test tray TST₁ beingstopped at an unloader section 400 of the handler part, a test tray TST₂being stopped at a loader section 300, and an IC detecting sensor 500provided between the unloader section 400 and the loader section 300 areshown. This IC detecting sensor 500 serves to detect whether or not anIC is left on each of the IC carriers 16 (see FIG. 6) mounted to thetest tray TST.

[0078] In this embodiment, there is shown a case in which a plurality oflight transmission type IC detecting sensors 500 each comprising a lightsource 501 and a photodetector 502 are disposed between the unloadersection 400 and the loader section 300 such that the light source 501and the photodetector 502 of each sensor 500 are opposed to each otherwith a plane through which a test tray TST passes put therebetween, andaligned in the direction orthogonal to the moving direction of the testtray TST, thereby to detect whether or not an IC is left on the testtray TST passing through the plane.

[0079] The IC detecting sensor 500 is provided corresponding to thenumber of lines (the number of transverse rows along the movingdirection of the test tray) of the IC carriers 16 mounted to the testtray TST. That is, when the number of carriers 16 mounted to the testtray TST aligned in the direction orthogonal to the moving direction ofthe test tray TST (in the direction of a longitudinal row) is four (thenumber of lines is four) as shown, four IC detecting sensors 500 may bearranged at a pitch that is an interval between the four IC carriers 16aligned in the direction of the longitudinal row. In the illustratedexample, the light sources 501 are provided on the upper side of theplane through which the test tray passes, and the photodetectors 502 areprovided on the lower side of the plane through which the test traypasses. The light sources 501 and the photodetectors 502 may be, ofcourse, arranged in the reverse relation.

[0080] An aperture (through-hole) 16A is formed in a bottom plate ofeach IC carrier 16 as shown in FIG. 12. The photodetector 502 detectslight passing through the aperture 16A. Since there is an openingthrough which light from the light source 501 passes (an opening throughwhich pins of an IC loaded on the IC carrier 16 are exposed or the like)in the bottom plate of each IC carrier 16, only the light passingthrough the aperture 16A must be detected by the photodetector 502. Forthis purpose, as illustrated in FIG. 13 in enlarged size, reflectivemarks 503A are affixed, for instance, on one of the sides of therectangular frame 12 of the test tray TST running parallel to the movingdirection of the test tray TST, the reflective marks 503A being appliedto positions of the one side of the rectangular frame 12 correspondingto the positions of the apertures 16A of the bottom plates of a set ofthe IC carriers 16 aligned in the moving direction of the test tray inthis embodiment. Each of the reflective marks 503A has its size orlength in the moving direction selected to be equal to or a littlelonger than the diameter of corresponding one of the apertures 16A ofthe bottom plates of a set of the IC carriers 16 aligned in the movingdirection of the test tray. In this embodiment, the rectangular frame 12of each test tray is made of a non-reflective material, and henceportions of the rectangular frame 12 on which the reflective marks 503Aare not affixed serve as non-reflective marks 503B. Accordingly, areflection type optical sensor 504 is located above the test tray anddetects light emitted from the optical sensor 504 and reflected from oneof the reflective marks 503A. With the construction as described above,only the light passing through the aperture 16A can be detected therebydetecting the presence of an IC on the test tray depending upon whetherthe IC detecting sensor 500 detects light or not while the opticalsensor 504 is detecting light reflected from one of the reflective marks503A.

[0081] In the aforementioned embodiment, there is explained a case ofdetecting whether or not an IC remains on a test tray transported fromthe unloader section 400 to the loader section 300. However, analternative arrangement is also possible in which IC detecting sensors500 are positioned, for example, midway on the path from the loadersection 300 to the tester head 104 as well as midway on the path fromthe tester head 104 to the unloader section 400. With such arrangement,it is possible to detect an empty IC pocket in a test tray resultingfrom that an IC is dropped out of the test tray while the test tray istransporting from the loader section 300 to the tester head 104 can bedetected. Also, it is possible to detect an empty IC pocket in the testtray resulting from that an IC is dropped out of the test tray duringthe test on the tester head 104.

[0082] It is possible to improve the reliability of the IC testingapparatus by providing the IC detecting sensors 500 at any one of thepositions as stated above. However, in case the IC detecting sensors 500are provided at both positions between the unloader section 400 and theloader section 300 and between the tester head 104 and the unloadersection 400, or at both positions between the unloader section 400 andthe loader section 300 and between the loader section 300 and the testerhead 104, the reliability of the IC testing apparatus can be furtherimproved. It is needless to say that if the IC detecting sensors 500 areprovided at all the above positions, the reliability of the IC testingapparatus can be improved most.

[0083] Further, the relationship of disposition between the reflectivemarks 503A and the non-reflective marks 503B may be reversed from thestate shown in FIG. 13 so that only the light passing through theaperture 16A can be detected thereby detecting the presence of an IC onthe test tray depending upon whether the IC detecting sensor 500 detectslight or not while the optical sensor 504 is not detecting any reflectedlight.

[0084] In addition to the light transmission type IC detecting sensor, aproximity switch for detecting a metal (a metal in an IC) or a camerahaving a pattern recognition function or the like may be used as the ICdetecting sensor 500.

[0085] As explained above, according to the IC testing system of thefirst embodiment of the present invention, no classifying process of thetested ICs is required in the handler part 11. In addition, according tothe IC testing system of the second embodiment of the present invention,only a sorting operation of the tested ICS into two categories such aspass ICs and failure ICs or other suitable two categories is performedin the handler part 11. Therefore, the time interval required fortesting the ICs in each IC testing apparatus can be considerably reducedand the testing process can be executed at high speed. Further, even inthe second embodiment, only a classifying operation of the tested ICsinto two categories may be performed in the handler part 11, andtherefore, the configuration or construction of the handler part can besimplified. Consequently, the cost of the handler part 11 can bereduced. In addition, since the data stored in the storage informationmemory means includes the number of a socket with which an IC under testis brought into contact in the test section, if failure ICs areconcentrated in the tested ICs having contacted with a specified socket,the socket can be presumed to be defective. Therefore, there is anadvantage that failure of sockets in the test section can be detected.Moreover, since the dedicated classifying machine 3 performs onlyclassifying operation, it can be manufactured at low cost. Consequently,there is an there is an advantage that a low cost IC testing system canbe constructed on the whole.

[0086] In addition, according to the IC testing apparatus of the firstembodiment of the present invention, a feature for detecting an ICremaining on a test tray TST which should have been emptied of thetested ICs is added thereto. Therefore, it is possible to prevent fromoccurring in the loader section 300 an erroneous operation that an IC isloaded on the remaining IC in the form of a stack. Consequently, anaccident can be prevented that, for example, an IC drops out of the testtray in the constant temperature chamber 101 whereby a transportingapparatus located therebelow can be damaged. In addition, an erroneousclassification can be prevented that the upper IC in the stack istransported without being dropped out of the test tray, is tested, andis discharged to the unloader section 400 where the upper IC is sortedout on the basis of the test results of the lower IC in the stack.

[0087] Further, according to the IC testing apparatus of the secondembodiment of the present invention, even if an IC drops from the testtray during the test in the test section or during the transportationtime of the test tray from the test section to the unloader section 400,the dropping of the IC can be detected. Therefore, an erroneousoperation can be prevented that an IC is virtually classified from theIC pocket on the test tray in which any IC is absent in accordance withthe test results stored in the memory means. That is, a classifyingoperation with respect to the IC pocket on the test tray in which no ICexists can be eliminated and the time required for the entireclassifying operation can be reduced.

[0088] In addition, according to the IC testing apparatus of the thirdembodiment of the present invention, even if an empty IC pocket existson a test tray TST transported to the test section due to a case that anIC is dropped out of the test tray during the transportation time of thetest tray from the loader section 300 to the test section, or that thetest tray is transported to the test section with an IC pocket emptiedof an IC because an IC to be tested could not have been loaded on thetest tray in the loader section 300, this empty IC pocket can bedetected. Therefore, the test for the empty IC pocket can be eliminated.As a result, a wasteful test is not performed, and so the testing timecan be reduced and a high reliable IC testing apparatus can be provided.

[0089] While the present invention has been described in the above asbeing applied to the IC testing apparatus for testing ICs assemiconductor devices, it is needless to say that the present inventionis also applicable to testing apparatus for testing semiconductordevices other than ICs, and the same effects are obtained as describedabove.

What is claimed is:
 1. A semiconductor device testing system comprisinga semiconductor device testing apparatus having a tester part and ahandler part, storage information memory means, and a dedicatedclassifying machine, and wherein a plurality of semiconductor devices tobe tested are transferred from a general-purpose tray to a test tray tobe reloaded thereon in a loader section of said handler part, said testtray is transported into a test section of the handler part where saidsemiconductor devices loaded on said test tray are brought intoelectrical contact with a tester head of said tester part disposed insaid test section to test operation of the semiconductor devices, afterthe completion of the test, said test tray with the tested semiconductordevices loaded thereon is transported from the test section to anunloader section of the handler part where the tested semiconductordevices on said test tray are transferred from said test tray onto ageneral-purpose tray, and the general-purpose tray with the testedsemiconductor devices loaded thereon is taken out of said handler part,said semiconductor device testing system being characterized in: that intransferring the tested semiconductor devices on the associated testtray from the test tray onto a general-purpose tray in said unloadersection, storage information of respective tested semiconductor devicessuch as a number assigned to each semiconductor device, the test resultsof each semiconductor device, the number of a socket used in testing theassociated semiconductor device in said test section, and the like isstored in said storage information memory means every time each testedsemiconductor device is stored in a semiconductor device storage portionof one general-purpose tray; that said storage information stored insaid storage information memory means is transmitted to said dedicatedclassifying machine; and that the tested semiconductor devices aresorted out using said dedicated classifying machine on the basis of saidtest results.
 2. A semiconductor device testing system comprising asemiconductor device testing apparatus having a tester part and ahandler part, storage information memory means, and a dedicatedclassifying machine, and wherein semiconductor devices to be tested aretransported into a test section of said handler part where saidsemiconductor devices are brought into electrical contact with a testerhead of said tester part disposed in said test section to test operationof the semiconductor device, and after the completion of the test, thetested semiconductor devices are transported from the test section to anunloader section of said handler part where the tested semiconductordevices are sorted out on the basis of the test results of thesemiconductor devices and stored in semiconductor device storagesection, said semiconductor device testing system being characterizedin: that in said unloader section, only a sorting operation of thetested semiconductor devices into two categories of conformable or passarticles and unconformable or failure articles is performed; thatstorage information of respective tested semiconductor devices stored insaid semiconductor device storage section such as the test results ofeach semiconductor device, a number assigned to each semiconductordevice, the number of a socket used in testing the associatedsemiconductor device in said test section, and the like is stored insaid storage information memory means; that said storage informationstored in said storage information memory means is transmitted to saiddedicated classifying machine; and that the tested semiconductor devicesare further subclassified using said dedicated classifying machine onthe basis of said test results.
 3. A semiconductor device testing systemcomprising a plurality of semiconductor device testing apparatus eachhaving a tester part and a handler part, each semiconductor devicetesting apparatus being arranged such that semiconductor devices to betested are transported into a test section of said handler part wheresaid semiconductor devices are brought into electrical contact with atester head of said tester part disposed in said test section to testoperation of the semiconductor device, and after the completion of thetest, the tested semiconductor devices are transported from the testsection to an unloader section of said handler part where the testedsemiconductor devices are sorted out on the basis of the test results ofthe semiconductor devices and stored in semiconductor device storagesection, and wherein said plurality of semiconductor device testingapparatus have different test conditions from one another, andsemiconductor devices to be tested are transported to said plurality ofsemiconductor device testing apparatus in order and sequentially undergotests under the different test conditions in said plurality ofsemiconductor apparatus, said semiconductor device testing system beingcharacterized in: that in said unloader section, only a sortingoperation of the tested semiconductor devices into two categories ofconformable or pass articles and unconformable or failure articles isperformed; and that only the tested semiconductor devices which havebeen determined to be pass articles are transported to the subsequentsemiconductor device testing apparatus for testing.
 4. The semiconductordevice testing system according to claim 3, wherein each of saidplurality of semiconductor device testing apparatus further includesstorage information memory means and a dedicated classifying machine,and storage information of respective tested semiconductor devicesstored in said semiconductor device storage section such as the testresults of each semiconductor device, a number assigned to eachsemiconductor device, the number of a socket used in testing theassociated semiconductor device in said test section, and the like isstored in said storage information memory means, and upon completion ofall the tests said storage information stored in said storageinformation memory means is transmitted to said dedicated classifyingmachine, and the tested semiconductor devices are further subclassifiedusing said dedicated classifying machine on the basis of said testresults.
 5. A semiconductor device testing apparatus having a testerpart and a handler part, and wherein semiconductor devices to be testedare transferred from a general-purpose tray to a test tray to bereloaded thereon in a loader section of said handler part, said testtray is transported into a test section of said handler part to test thesemiconductor devices, after the completion of the test, said test traywith the tested semiconductor devices loaded thereon is transported fromsaid test section to an unloader section of said handler part where thetested semiconductor devices on said test tray are transferred from saidtest tray onto a general-purpose tray, and the test tray which has beenemptied of the tested semiconductor devices is transported from saidunloader section to said loader section, and the above operation isrepeated, said semiconductor device testing apparatus beingcharacterized in: that on the way of the carrying path of the test traybetween said unloader section and said loader section is provided asemiconductor device detecting sensor for monitoring whether asemiconductor device exists on the test tray or not; and that thepresence of any semiconductor device having been left on the test traytransported from said unloader section to said loader section can bedetected by said semiconductor device detecting sensor.
 6. Asemiconductor device testing apparatus having a tester part and ahandler part, and wherein semiconductor devices to be tested aretransferred from a general-purpose tray to a test tray to be reloadedthereon in a loader section of said handler part, said test tray istransported into a test section of said handler part to test thesemiconductor devices, after the completion of the test, said test traywith the tested semiconductor devices loaded thereon is transported fromsaid test section to an unloader section of said handler part where thetested semiconductor devices on said test tray are transferred from saidtest tray onto a general-purpose tray, and the test tray which has beenemptied of the tested semiconductor devices is transported from saidunloader section to said loader section, and the above operation isrepeated, said semiconductor device testing apparatus beingcharacterized in: that on the way of the carrying path of the test traybetween said test section and said unloader section is provided asemiconductor device detecting sensor for monitoring whether asemiconductor device exists on the test tray or not; and that thepresence of any empty semiconductor device receiving portion having nosemiconductor device therein in the test tray transported from said testsection to said unloader section can be detected by said semiconductordevice detecting sensor.
 7. A semiconductor device testing apparatushaving a tester part and a handler part, and wherein semiconductordevices to be tested are transferred from a general-purpose tray to atest tray to be reloaded thereon in a loader section of said handlerpart, said test tray is transported into a test section of said handlerpart to test the semiconductor devices, after the completion of thetest, said test tray with the tested semiconductor devices loadedthereon is transported from said test section to an unloader section ofsaid handler part where the tested semiconductor devices on said testtray are transferred from said test tray onto a general-purpose tray,and the test tray which has been emptied of the tested semiconductordevices is transported from said unloader section to said loadersection, and the above operation is repeated, said semiconductor devicetesting apparatus being characterized in: that on the way of thecarrying path of the test tray between said loader section and said testsection is provided a semiconductor device detecting sensor formonitoring whether a semiconductor device exists on the test tray ornot; and that the presence of any emptied semiconductor device receivingportion having no semiconductor device therein in the test traytransported from said loader section to said test section can bedetected by said semiconductor device detecting sensor.
 8. Thesemiconductor device testing apparatus according to claim 5, wherein onthe way of the carrying path of the test tray between said test sectionand said unloader section is provided a further semiconductor devicedetecting sensor for monitoring whether a semiconductor device exists onthe test tray or not.
 9. The semiconductor device testing apparatusaccording to claim 5, wherein on the way of the carrying path of thetest tray between said loader section and said test section is provideda further semiconductor device detecting sensor for monitoring whether asemiconductor device exists on the test tray or not.
 10. Thesemiconductor device testing apparatus according to claim 5, wherein onthe way of the carrying path of the test tray between said test sectionand said unloader section is provided a further semiconductor devicedetecting sensor for monitoring whether a semiconductor device exists onthe test tray or not, and on the way of the carrying path of the testtray between said loader section and said test section is provided astill further semiconductor device detecting sensor for monitoringwhether a semiconductor device exists on the test tray or not.
 11. Thesemiconductor device testing apparatus according to any one of claims 5to 10, wherein the number of said semiconductor device detecting sensoris equal to that of the semiconductor device receiving portions on thetest tray which are aligned in a direction perpendicular to the movingdirection of the test tray, and each sensor is an optical sensor fordetecting transmitted light.
 12. The semiconductor device testingapparatus according to any one of claims 5 to 10, wherein the number ofsaid semiconductor device detecting sensor is equal to that of thesemiconductor device receiving portions on the test tray which arealigned in a direction perpendicular to the moving direction of the testtray, and further including a reflected light detecting type opticalsensor for detecting reflected light, and wherein said reflected lightdetecting type optical sensor detects a reflective mark ornon-reflective mark provided on the frame of the test tray and thepresence of a semiconductor device on the test tray is determined by asignal detected by and outputted from said semiconductor devicedetecting sensor in synchronism with the reflective mark ornon-reflective mark detected by said reflected light detecting typeoptical sensor.
 13. The semiconductor device testing apparatus accordingto claim 12, wherein said reflective or non-reflective mark is providedon one side of the frame of the test tray, said one side of the framebeing parallel to the moving direction of the test tray and saidreflective or non-reflective mark being provided on the positions ofsaid one side corresponding to the central portions of the respectivesemiconductor device receiving portions in the test tray which arealigned in the moving direction of the test tray.